 Courses and Research Papers and Articles University Courses • MIT Course: 6.375 - Complex Digital Systems(Spring 2009) • MIT Course: 6.827 - Multithreaded Parallelism: Languages and Compilers • MIT Course: 6.884 - Complex Digital Systems (MIT OpenCourseWare version) • CMU Course: 18-744 - Hardware Systems Engineering • LUND University Course: EDA385 - Embedded System Design Third-Party Designs Available through OpenCore • OFDM (Note that this project is not yet available on OpenCores so an alternative link is provided) • MD6 • H.264 Bluespec Workshop • First Workshop, August 2007, Workshop Website Applications of Bluespec • Eric S. Chung, Michael K. Papamichael, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi and Ken Mai. “ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs”, to appear in ACM Transactions on Reconfigurable Technology and Systems, 2009. • Kattamuri Ekanadham; Jessica Tseng; Pratap Pattnaik. “IBM PowerPC Design in Bluespec”, published in: RC24706 in 2008 • Abhinav Agarwal, Man Cheuk Ng, Arvind. “Comparison of high level design methodologies for algorithmic IPs: Bluespec and C-based synthesis”, MIT Computer Science and Artificial Intelligence Laboratory (CSAIL) • Fleming, Elliott. Hardware reference design for MD6, October 2008. • K.Ekanadham, N.Greco, P.Pattnaik, J.Tseng, Arvind, A.Khan, M.Vijayaraghavan and A.Yamhure.“The IBM/MIT PowerPC Project”, Presentation at RAMP Retreat, Stanford University, August 2008. • Angshuman Parashar, Michael Adler, Michael Pellauer, Joel Emer. Hybrid CPU/FPGA Performance Models”, WARP 2008, June, 2008. • April 2008 Gruian, F. and Westmijze, M. “VHDL vs. Bluespec system verilog: a case study on a Java embedded architecture”, in Proceedings of the 2008 ACM Symposium on Applied Computing (Fortaleza, Ceara, Brazil, March 16 - 20, 2008). SAC '08. ACM, New York, NY, 1492-1497. • Eric S. Chung, Eriko Nurvitadhi, James C. Hoe, Babak Falsafi and Ken Mai. “A Complexity-Effective Architecture for Accelerating Full-System Multiprocessor Simulations Using FPGAs”, International Symposium on Field Programmable Gate Arrays (FPGA), February 2008. (pdf) • FAST team. “Video of FAST simulator running Microsoft Word on Windows XP”.
• Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William Reinhart, D. Eric Johnson, Jebediah Keefe and Hari Angepat. “FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators”, MICRO 2007. • Derek Chiou, Dam Sunwoo, Joonsoo Kim, Nikhil A. Patil, William H. Reinhart, D. Eric Johnson and Zheng Xu. “The FAST Methodology for High-Speed SoC/Computer Simulation”, Proceedings of International Conference on Computer-Aided Design (ICCAD), November 2007. • Gruian, F. and Westmijze, M. “BluEJAMM: A Bluespec Embedded Java Architecture with Memory Management”, In Proceedings of the Ninth international Symposium on Symbolic and Numeric Algorithms For Scientific Computing (September 26 - 29, 2007). SYNASC. IEEE Computer Society, Washington, DC, 459-466. DOI= http://dx.doi.org/10.1109/SYNASC.2007.12 • Man Cheuk Ng, Muralidaran Vijayaraghavan, Gopal Raghavan, Nirav Dave, Jamey Hicks, Arvind. “From WiFI to WiMAX: Techniques for IP Reuse Across Different OFDM Protocols”, Formal Methods and Models for Codesign (MEMOCODE 2007), Nice, France, May 2007 • Nirav Dave, Kermin Fleming, Myron King, Michael Pellauer, Muralidaran Vijayaraghavan. “Hardware Accelleration of Matrix Multiplication on a Xilinx FPGA”, Formal Methods and Models for Codesign (MEMOCODE 2007), Nice, France. May 2007 • Chun-Chieh Lin, "Implementation of H.264 Decoder in Bluespec System Verilog", Masters Thesis, February, 2007 • Nirav Dave, Michael Pellauer, Steve Gerding, and Arvind. “802.11a Transmitter: A Case Study in Michroarchitectural Exploration”, in the proceedings of Formal Methods and Models for Codesign (MEMOCODE'2006), Napa, CA, July 26-30, 2006 • Arvind, Jan-Willem Maessen. “Memory Model = Instruction Reordering + Store Atomicity”, presented at ISCA 2006, The 33rd Annual International Symposium on Computer Architecture, Boston, MA USA , June 17-21, 2006. • Nirav Dave, Michael Pellauer,Arvind, Joel Emer. "Implementing a Functional/Timing Partitioned Microprocessor Simulator with an FPGA", 2nd Workshop on Architecture Research using FPGA Platforms, February 2006. • Nirav Dave, Man Cheuk Ng, Arvind. “Automatic Synthesis of Cache-Coherence Protocol Processors Using Bluespec”, Formal Methods and Models for Codesign (MEMOCODE'2005), Verona, Italy, July 11-14, 2005.
• Arvind, Rishiyur S. Nikhil, Daniel Rosenband, Nirav Dave. “High-Level Synthesis: An Essential Ingredient for Designing Complex ASICs”, International Conference on Computer Aided Design (ICCAD 2004), San Jose, CA, November 6-10, 2004. • Roland E. Wunderlich, James C. Hoe. “In-System FPGA Prototyping of an Itanium Microarchitecture”, International Conference on Computer Aided Design (ICCAD), October 2004. • Nirav Dave. “Designing a Reorder Buffer in Bluespec”, MIT Computer Science and Artificial Intelligence Lab, International Conference on Formal Methods and Models for Codesign (MEMOCODE 2004), San Diego, CA, June 22-25, 2004. • Rishiyur S. Nikhil. “Future Programming of FPGAs”, FPGA 2004 Panel, February 23, 2004. • Arvind. “Why Chip Design Can’t Be Left to EEs”, MIT Computer Science and Artificial Intelligence Lab, 2004. • Joydeep Ray, James C. Hoe. “High-Level Modeling and FPGA Prototyping of Microprocessors”, International Symposium on Field Programmable Gate Arrays (FPGA), February 2003.
• Xiaowei Shen. “Design and Verification of Adaptive Cache Coherence Protocols" – Ph.D. Thesis, MIT Computer Science and Artificial Intelligence Lab, January 2000. • James C. Hoe, Arvind. “Deriving Superscalar Microarchitectures from Pipelined Microarchitectures”, November, 1999 • Arvind, Xiaowei Shen. “Using Term Rewriting Systems to Design and Verify Processors”, IEEE Micro, 19:3, pp 36-46, May 1999. • Lisa Poyneer, James C. Hoe, Arvind. “A TRS Model for a Modern Microprocessor”, MIT Computer Science and Artificial Intelligence Lab, June 1998. Core Technology • Gaurav Singh and Sandeep K. Shukla. “Verifying Compiler Based Refinement of Bluespec System Verilog Specifications using the SPIN Model Checker”, selected for presentation in Workshop on 'High-level Synthesis: Back to the Future' in Design Automation Conference (DAC), 2008. • Gaurav Singh and Sandeep K. Shukla. “Power Reduction Techniques for Hardware Synthesis for High-Level BSV Specifications”, selected for presentation in Workshop on 'High-level Synthesis: Back to the Future' in Design Automation Conference (DAC), 2008. • Gaurav Singh and Sandeep K. Shukla. “Verifying Compiler Based Refinement of Bluespec Specifications using the SPIN Model Checker”, 15th International SPIN Workshop on Model Checking (SPIN), 2008. • Nirav Dave, Arvind, Michael Pellauer. “Scheduling as Rule Composition”, Formal Methods and Models for Codesign (MEMOCODE 2007), Nice, France, May 2007 • Gaurav Singh, Jacob B. Schwartz, Sumit Ahuja and Sandeep K. Shukla. “Techniques for Power-aware Hardware Synthesis from Concurrent Action Oriented Specifications”, Journal of Low Power Electronics (JOLPE), 2007. • Gaurav Singh and Sandeep K. Shukla. “Model-checking based Verification for Hardware Designs specified using Bluespec System Verilog”, 8th International Workshop on Microprocessor Test and Verification (MTV), 2007. • Gaurav Singh and Sandeep K. Shukla. “Low-power hardware synthesis from TRS-based specifications”, 4th ACM and IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE), 2006. • Daniel L. Rosenband and Arvind. “Hardware Synthesis from Guarded Atomic Actions with Performance Specifications”, in the proceedings of International Conference on Computer Aided Design (ICCAD), San Jose, CA, Nov. 6-10, 2005 • Daniel L. Rosenband. “A Performance Driven Approach for Hardware Synthesis of Guarded Atomic Actions”, PhD Thesis, MIT, August, 2005 • Michael Pellauer, Massachusetts Institute of Technology, Mieszko Lis, Don Baltus, and Rishiyur Nikhil, Bluespec. “Synthesis of Synchronous Assertions with Guarded Atomic Actions”, Formal Methods and Models for Codesign (MEMOCODE'2005), Verona, Italy, July 11-14, 2005. • James C. Hoe, Arvind. “Operation-Centric Hardware Description and Synthesis”, IEEE TRANSACTIONS on Computer-Aided Design of Integrated Circuits and Systems, Volume 23, Issue 9, September 2004. • Grace Nordin, James C. Hoe. “Synchronous Extensions to Operation-Centric Hardware Description Languages”, International Conference on Formal Methods and Models for Codesign (MEMOCODE), San Diego, CA, June 22-25, 2004. • Daniel Rosenbrand. “The Ephemeral History Register: Flexible Scheduling for Rule-Based Designs”, MIT Computer Science and Artificial Intelligence Lab, International Conference on Formal Methods and Models for Codesign (MEMOCODE 2004), San Diego, CA, June 22-25, 2004. • Daniel Rosenband, Arvind. “Modular Scheduling of Guarded Atomic Actions”, 41st Design Automation Conference (DAC), San Diego, CA, June 2004. • Arvind, Daniel Rosenband, Jacob Schwartz. “Modular Scheduling of Atomic Actions”, MIT Computer Science and Artificial Intelligence Lab, April 2004. • Arvind. “Bluespec: A Language for hardware design, simulation, synthesis and verification”, Extended Abstract, Proceedings of MEMOCODE, ACM, June 2003. • Arvind, Daniel Rosenband, Jacob Schwartz. “Computer Architecture Modeling, Synthesis, and Verification”, MIT Computer Science and Artificial Intelligence Lab, March 2003. • James C. Hoe, Arvind. “Synthesis of Operation-Centric Hardware Descriptions”, International Conference on Computer Aided Design (ICCAD), San Jose, California, November 2000. • James C. Hoe. “Operation-Centric Hardware Description and Synthesis”, PhD Thesis, MIT, June 2000. • James C. Hoe, Arvind. “Hardware Synthesis from Term Rewriting Systems”, IFIP International Conference on VLSI, December 1999. • Xiaowei Shen, Arvind, Larry Rudolph. “CACHET: An Adaptive Cache Coherence Protocol for Distributed Shared-Memory Systems”, Proceedings of the 26th International Symposium on Computer Architecture, Atlanta, Georgia, May 1999. • Xiaowei Shen, Arvind, Larry Rudolph. “Commit-Reconcile and Fences (CRF): A New Memory Model for Architects and Compiler Writers ”, Proceedings of the 26th International Symposium on Computer Architecture, Atlanta, Georgia, May 1999. • Xiaowei Shen, Arvind. “Design and Verification of Speculative Processors”, Proceedings of the Workshop on Formal Techniques for Hardware and Hardware-like Systems Architecture, Marstrand, Sweden, June 1998. • Xiaowei Shen, Arvind. “A Methodology for Designing Correct Cache Coherence for DSM Systems”, MIT Computer Science and Artificial Intelligence Lab, March 1998. • Xiaowei Shen, Arvind. “Modeling and Verification of ISA Implementations”, Proceedings of the Australasian Computer Architecture Conference, Perth, Australia Architecture, February 1998. • Xiaowei Shen, Arvind. “An Adaptive Cache Coherence Protocol That Implements Sequential Consistency for DSM Systems with Multi-level Caches”, MIT Computer Science and Artificial Intelligence Lab, December 1997. • Xiaowei Shen, Arvind. “Specification of Memory Models and Design of Provably Correct Cache Coherence Protocols”, MIT Computer Science and Artificial Intelligence Lab, January 1997. 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