Whitepaper:
 
High-level "plug and play" specification, modeling and synthesis of algorithms using Bluespec's PAClib
 

IFFT in 100 lines of code, generating 24 micro-architectures for FPGAs and ASICs
test bench

What if you could create a single specification for an algorithm that could automatically generate many different architectures?

What if this single specification could seamlessly encompass datapath and complex control applications?

What if this single specification, unlike C/C++/SystemC, kept you 100% in control of and provided 100% transparency to the architectures it could generate?

What if this specification enabled you to use a fully extensible plug-and-play library of parameterized pipeline building blocks that allow architecture and computational concerns to be easily separated?

Abstract:

It is commonly assumed that the route to high-level specification and synthesis goes through C/C++/ SystemC, particularly for “algorithmic” or “datapath oriented” applications. This white paper presents a more effective and proven alternative. Starting with the basic computational functions of an application, one can build complex pipeline architectures in an easy “plug and play” manner by systematically composing powerful constructors from Bluespec's PAClib (Pipelined Architecture Composers library). The high level, yet transparent and precise specification of the desired pipeline architecture quickly and predictably results in high quality implementations. Moreover, parametrization permits writing a single source code to encompass a wide variety of architectural choices, each of which may be more appropriate for different targets (e.g., mobile device vs. server). The technique relies on the advanced types, parametrization and atomic rule-based semantics of BSV (Bluespec SystemVerilog), unavailable in other design languages. BSV is also universal, seamlessly encompassing both datapath and control-oriented applications, whereas C/C++ high-level synthesis mostly applies to the former. Further, unlike C/C++, everything in BSV is synthesizable, so all refinements from initial models to final implementations can be executed on hardware platforms (e.g., FPGA/emulation) at speeds orders of magnitude faster than the best software simulators, greatly benefiting validation, verification and early software development.

This white paper demonstrates these capabilities using the example of Inverse Fast Fourier Transform (IFFT), an important function in many wireless protocols that admits a rich space of architectures.