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Emulation Infrastructure
What if you could leverage emulation early for system exploration and validation as well as firmware development – even before RTL is ready?
Synthesizable transactors are challenging to develop, which diverts development focus from core project activities and puts schedule at risk. Bluespec has a library of common transactors that can be used right off-the-shelf – and, if you need something different, Bluespec has the industry’s best solution for developing your own. The Bluepsec transactor library includes popular bus interfaces like AMBA AXI, AHB and APB, communication I/O interface protocols like Ethernet and PCIe, and functions like console/UART and large, parameterized memory models. With these you quickly and easily connect your host-based verification environments to your design-under-test. Not in our library? Don’t get bogged down by RTL. Developing synthesizable transactors in RTL is really hard and takes a long time – and developing highly flexible, reusable ones is next to impossible. Bluespec synthesizable modeling is the solution of choice for leading semiconductor and system companies developing synthesizable transactors. Unlike any other high-level synthesis, you get easy expression of the complex control and interconnects that are typically found in transactor – in addition to its ability to tackle algorithms. Plus you can parameterize on almost any dimension, for better re-use, while still staying 100% synthesizable. And, Bluespec has a rich set of tools to accelerate the design and debug of transactors in emulation, even on the desktop. Synthesizable System Models In order to fully exercise a design, you may need to flesh out your verification environment with system models, such as disk drives or USB devices. Or you may want to develop a golden reference model – or use model in advance of RTL being ready for a block. If you are targeting emulation or FPGA prototyping, why get stuck with RTL or, worse yet, doing without? Bluespec synthesizable modeling lets you quickly develop these types of models – from functional to cycle-accurate – at a high-level for any type of system-level device, including complex control, interconnects and algorithms. All of these are 100% synthesizable into emulation or FPGA prototyping. Synthesizable Test Benches You no longer develop complex test benches with RTL. Why should you have to when you target emulation and FPGA prototyping? High-level verification languages and environments such as SystemVerilog and e/Specman, as used in VMM or OVM, may be the state-of-the-art for writing test bench IP, but they are useless for developing models, transactors and test benches to run in FPGAs for emulation and prototyping. None of these languages are synthesizable. So engineers wishing to move verification assets onto FPGAs have been designing with RTL, the same old slow, resource-intensive and error-prone way. With BSV, Bluespec offers the industry’s best-in-class high-level synthesis language, toolset and set of IP libraries that enable powerful parameterization, reusability, and composability for modeling, verification and implementation. Bluespec provides the only general-purpose, high-level synthesis toolset for any use model (models, test benches, production IP) and design type (datapath, control, interconnect). Use BSV to develop high flexible traffic generators, analyzers, monitors and much more that can run in emulation and prototyping. Instrumentation & Debug Instrumentation and debug in emulation and FPGA prototyping environments can be a serious challenge. Bluespec provides solutions that enable the instrumentation, control and debug of synthesizable models and DUTs running in emulation. Run billions of cycles in seconds and then debug with the 100% visibility of simulation environments. Bluespec also provides an industry standard co-emulation (SCE-MI) solution that can be optionally used for connecting software-based test benches and models with designs running in emulation. |
