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Author
Views
Last Post
sce-mi
1
madhav
260
Mon Aug 02, 2010 8:19 pmjnewbern
Data Flow modelling question
0
TheSheriff
329
Thu Jun 10, 2010 1:22 amTheSheriff
tradeoffs when using Real, Complex, or Math libraries
2
TheSheriff
358
Thu Jun 10, 2010 1:01 amTheSheriff
how to convert Bit#(n) to Integer?
1
roMoon
345
Wed Jun 02, 2010 9:32 amjnewbern
sce_mi pcie example
1
azeng
453
Fri May 07, 2010 3:13 pmcrimsoncardinal
SCE-MI USB example
1
dragoscsit
511
Fri Apr 23, 2010 12:10 pmjnewbern
FSM Problem
2
justrajdeep
753
Wed Apr 21, 2010 3:11 pmbaltus
Prelude.bs error
3
hrishikesh
2095
Fri Mar 19, 2010 1:45 pmquark
Is it BSV support condition compile?
3
test002
583
Mon Mar 15, 2010 11:18 pmtest002
how to peform shift left or right operation ?
4
tyeowkwa
619
Thu Mar 11, 2010 5:20 pmtyeowkwa
Instruction set to memory
5
tyeowkwa
900
Wed Mar 03, 2010 8:06 amjnewbern
Multiple Resets
0
kirubi
648
Thu Jan 28, 2010 5:18 amkirubi
Pack/Unpack functions
2
muem
812
Wed Jan 27, 2010 11:44 ammuem
problem about method
1
jarronshih
838
Wed Jan 20, 2010 10:40 amjnewbern
a doubt in Register array
5
patanjali
1569
Wed Jan 20, 2010 10:16 amjnewbern
SBOX with two indices
0
muem
672
Tue Jan 12, 2010 5:20 ammuem
Multiple-clocks and ancestor_of attributes
0
kirubi
755
Tue Dec 29, 2009 10:56 amkirubi
Resets
3
kirubi
1001
Mon Dec 28, 2009 10:37 pmquark
What does this error mean?
1
kirubi
802
Mon Dec 28, 2009 2:34 pmquark
conv_integer
8
kirubi
1896
Wed Dec 16, 2009 12:54 amkirubi
generating multiple clocks from a bsv module
2
kirubi
1345
Fri Nov 20, 2009 9:31 pmjnewbern
Active high reset?
2
aaronsev
1310
Tue Oct 20, 2009 10:27 pmaaronsev
deriving Bits on a tagged union
2
patil.nikhil
1497
Mon Sep 28, 2009 5:53 pmpatil.nikhil
method ordering
1
patil.nikhil
1324
Fri Sep 25, 2009 7:25 ampatil.nikhil
flipflop design with register as a clock
2
dcelia
1769
Thu Sep 17, 2009 4:54 amtest001
deriving polymorphic interfaces
1
adarsh
1443
Thu Aug 20, 2009 1:59 pmquark
Simulation of design
3
nilay05
1982
Tue Aug 18, 2009 10:30 amquark
How to connect one module to another module?
0
nilay05
1239
Tue Aug 18, 2009 2:43 amnilay05
More than one return statements in one method
2
nilay05
1500
Fri Aug 14, 2009 1:05 pmquark
Generation of clock and reset in verilog
5
nilay05
2668
Mon Aug 10, 2009 3:22 pmhadar_agam
Attributes
1
nilay05
1438
Sat Aug 01, 2009 2:33 pmquark
testbench!!!!!!!!!!!!
7
tillu
3302
Tue Jul 28, 2009 10:35 amquark
Asynchronous designs
1
dcelia
1451
Mon Jul 13, 2009 4:29 pmquark
How to synthesize the generated verilog codes from bluespec
1
kireeti
1515
Mon Jun 22, 2009 10:41 pmtest001
More than one Asynchronous conditions for a register!!!
0
Neel
1404
Sat Jun 13, 2009 9:15 amNeel
bidirectional buffer
1
dcelia
1604
Tue Jun 09, 2009 2:03 pmdraenor
connecting the modules......
1
tillu
1659
Tue Jun 09, 2009 1:18 amdcelia
How to make communicate the Bluespec to systemC
4
jo.prakash
2484
Fri May 15, 2009 6:12 pmcrimsoncardinal
Interface and/or Struct Accessor Functions?
0
arielb
1509
Sun Apr 26, 2009 3:38 amarielb
Registers as Clocks
3
ask87
2236
Mon Apr 20, 2009 11:43 pmjnewbern
Storing Clock value in register
0
ask87
1463
Mon Apr 20, 2009 11:37 pmask87
sheduling.......
0
tillu
1492
Mon Apr 20, 2009 12:22 pmtillu
Warnings about bogus? cycles
2
geert
1928
Wed Apr 15, 2009 1:58 pmShepSiegel
modular exponential
0
tillu
1571
Wed Apr 08, 2009 3:16 amtillu
BRAM Question
4
kvb
2704
Tue Mar 31, 2009 11:05 amkvb
Type of value constructor?
2
arielb
2069
Wed Mar 25, 2009 6:07 amarielb
what does this error mean?
1
kaka
1706
Wed Mar 18, 2009 12:31 pmquark
FSM with One Rule
1
vitali
1802
Wed Mar 11, 2009 2:30 pmhadar_agam
Can enums be used to select a vector element?
6
geert
3086
Wed Mar 11, 2009 1:22 pmstoy
Contant expression: how to manipulate a numeric type
2
geert
2101
Fri Mar 06, 2009 11:02 pmjnewbern
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