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BSV Third-Party Papers

 
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crimsoncardinal



Joined: 25 Apr 2007
Posts: 66

PostPosted: Thu Nov 01, 2007 1:46 pm    Post subject: BSV Third-Party Papers Reply with quote

This topic is for particularly interesting and useful third-party papers. Attempts will be made to provide links to the paper where possible.
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crimsoncardinal



Joined: 25 Apr 2007
Posts: 66

PostPosted: Thu Nov 01, 2007 1:50 pm    Post subject: From WiFI to WiMAX: Techniques for IP Reuse Across Different Reply with quote

This is a terrific paper outlining how a single design can be parameterized to support multiple protocols and how micro-architectures can be parameterized -- including control-adaptivity (ability for the control logic to be automatically re-generated for a different micro-architecture).

If you're involved with OFDM (WiMax, WUSB, ....), this is an especially interesting paper.

It was published at Memocode 2007.

Here's the link to the paper off Nirav Dave's research page:

http://people.csail.mit.edu/ndave/Research/OFDM.pdf


Last edited by crimsoncardinal on Thu Nov 01, 2007 1:59 pm; edited 1 time in total
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crimsoncardinal



Joined: 25 Apr 2007
Posts: 66

PostPosted: Thu Nov 01, 2007 1:58 pm    Post subject: 802.11a Transmitter: A Case Study in Microarch. Exploration Reply with quote

This paper, using a WiFi transmitter design as an example, covers the rapid micro-architectural exploration of a complex datapath design. Bluespec enables the micro-architecture to be parameterized, including control-adaptivity (the control logic automatically gets generated for a new micro-architecture).

Here's a link to the paper:

http://csg.lcs.mit.edu/pubs/memos/Memo-495/memo495.pdf
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crimsoncardinal



Joined: 25 Apr 2007
Posts: 66

PostPosted: Thu Nov 01, 2007 2:09 pm    Post subject: High-Level Synthesis: An Essential Ingredient for... Reply with quote

High-Level Synthesis: An Essential Ingredient for Designing Complex ASICs

This paper reviews different implementations of an IP lookup function for a network processor. The key point of the paper is that it is very hard to understand the power/performance/area implications of a particular architectural approach without implementing it -- what you need therefore is an approach that allows one to do this rapidly.

This paper was presented at ICCAD 2004.

Here's a link to the paper: http://csg.csail.mit.edu/pubs/memos/Memo-473/memo473.pdf
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crimsoncardinal



Joined: 25 Apr 2007
Posts: 66

PostPosted: Thu Nov 01, 2007 2:17 pm    Post subject: Hardware Accelleration of Matrix Multiplication on a Xilinx Reply with quote

At the Memocode Conference 2007, there was a new contest focusing on hw/sw codesign. The problem involved matrix-matrix multiplication chosen in a way to force both a hardware and software component -- and targeted to run on a particular FPGA/processor platform. The goal was to partition and implement the highest performance solution.

Of the nine US and European teams that started -- only two finished. One used a more traditional methodology with a separate modeling and implementation approach -- the second (MIT) used Bluespec from the outset to model/prototype, re-architect/refine and explore (LOTS of exploration and changes). The Bluespec team's solution performed almost 500% better than the other solution.

Here's a link to the paper MIT did on their approach:

http://people.csail.mit.edu/ndave/Research/matrix_07.pdf

Here's a link to the contest summary and results:

http://www.ece.cmu.edu/~jhoe/distribution/mc07contest/
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crimsoncardinal



Joined: 25 Apr 2007
Posts: 66

PostPosted: Thu Nov 01, 2007 2:21 pm    Post subject: Implementation of H.264 Decoder in BSV Reply with quote

This was a thesis done by a master's student at MIT. Chun-Chieh single-handledly implemented an H.264 decoder implementation and got it up and running on a Xilinx FPGA. A couple interesting datapoints:

* It took him about 9 man-months to the first implementation running successfully on the FPGA

* His design is about 10,000 lines of code. NOTE: the C++ reference design, which is NOT synthesizable, is over 20,000 lines of code

Here's a link to his thesis:

http://csg.csail.mit.edu/pubs/memos/Memo-497/memo497.pdf
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