bluespec.com

[test001]

[jnewbern]

Test001,

This warning is telling you that when both rules fire together, you will see only the effects of one of the writes (whichever was scheduled later). In the particular example you've given the conditional inside the rule ensures that the writes will not actually happen in the same cycle, but the compiler does not analyze the conditionals inside the rule when generating the warning.

As the warning message says, you can disable it by using the -no-warn-action-shadowing flag.

Anyway, I would recommend against using ConfigReg in this way. I would caution you again that you appear to be fighting against the language instead of working with it. There are better ways to encode a state machine than as a separate set of rules manipulating a central step counter. Try StmtFSM, change your microarchitecture to expose some concurrent operations, or write your FSM in a single rule with a big case statement if you absolutely insist on using a low-level RTL-style encoding.

Regards,
Jeff

[test001]

Thank you!
I known StmtFSM is a good way, but I think write some examples for help verilog programmer to BluespecSystemVerilog.
So I try to rewrite tradition verilog to bsv with less modify.

This warning can off by command flag, but I do not think this a good way, I think not any warning in my code.
I try last night, at the end, I add the rule r3, it use a big 'case' to control variant step(and remove from r1 & r2), I can not get any warning now.