test001
Joined: 22 May 2008
Posts: 53
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 Posted: Tue Dec 30, 2008 10:15 pm Post subject: a bug when use flag "-unspecified-to" |
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| Code: | import Vector::*;
interface ITest;
method Action send(Bit#(8) data);
method Bit#(32) recv();
endinterface
(* synthesize *)
module test1( ITest );
Reg#(Vector#(4, Bit#(8))) vec <- mkReg(replicate(?));
method Action send(Bit#(8) data);
vec <= shiftInAt0(vec, data);
endmethod
method Bit#(32) recv();
return pack(vec);
endmethod
endmodule
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This is my small examples, I want to test ShiftReg in bsc output. I compile with | Code: | bsc -verilog -u -aggressive-conditions -unspecified-to 'X' test1.bsv"
or
bsc -verilog -u -aggressive-conditions -unspecified-to X test1.bsv"
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but in the verilog I will found
| Code: | if (!RST_N)
begin
vec <= `BSV_ASSIGNMENT_DELAY 32'hAAAAAAAA;
end
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This demo will use 18 slices in ISE, but when I change 32'hAAAAAAA to 'bX, 14 slices only.
I think here has a bug with flag '-unspecified-to'
btw: I known change "mkReg(replicate(?))" to "mkRegU" can solve this problem, but this may be a bug, so I report it. I think make value 'X' when unspecified is a good way in simulation between bsim & other. |
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