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BSV Application Notes

 
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kczeck



Joined: 30 Apr 2007
Posts: 68

PostPosted: Fri Apr 18, 2008 11:42 am    Post subject: BSV Application Notes Reply with quote

This topic contains application notes for using BSV.
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kczeck



Joined: 30 Apr 2007
Posts: 68

PostPosted: Fri Apr 18, 2008 11:47 am    Post subject: Using OCP/SystemC Channels with an Embedded Bluespec Model Reply with quote

The OCP foundation supplies standard libraries for implementing and interacting with OCP interfaces in SystemC models. This application note describes how to use these libraries with a BSV design which contains OCP interfaces or sub-interfaces, so that they can interact at the TLM-level with the SystemC environment in which they are embedded.

A SystemC model can be generated from a BSV design using the -systemc flag during the bsc link stage. The generated SystemC model has a clocked, signal-level interface which reflects the (flattened) top-level interface of the BSV design.



systemc-ocp.pdf
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SystemC-OCP application note

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kczeck



Joined: 30 Apr 2007
Posts: 68

PostPosted: Thu Sep 03, 2009 11:45 am    Post subject: Using RTL Models in Bluespec SystemVerilog Reply with quote

Existing RTL modules can be used as part of a Bluespec SystemVerilog (BSV) design. The BSV import "BVI" statement defines a Bluespec module wrapper for a Verilog or VHDL module, transcribing inputs and outputs into Bluespec interfaces and methods, along with scheduling annotations to fully describe the constraints of the module.

There are multiple ways to wrap any discrete RTL file depending on the model desired. This paper summarizes how to wrap a Verilog or VHDL module for use in a BSV design, and presents some design considerations along with options available to the designer.

This paper is also included in the tutorials section, along with source code examples.



importbvi.pdf
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Using RTL Models in Bluespec SystemVerilog (10/09)

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