Bluespec’s BSV high-level synthesis is completely different from C-based approaches. It’s not trying to weave gold out of the lead of sequential code. BSV is based on a unique, highly effective technology for abstracting hardware concurrency called atomic transactions. What does this give you?

• The industry’s only general-purpose, high-level synthesis solution that can handle any level of abstraction, from models to transactors to test benches to implementations, and any module type, as good for complex control and system interconnect as it is for algorithms
• 100% control over expressing architecture, which in the end is the most important driver of quality of results, for optimal power, performance, timing, area, latency or other
• Predictability and debugability – with 100% control over architecture, you not only get to RTL quickly, you can also meet specifications quickly too
• Atomic transactions dramatically simplify the expression of concurrent – while they enable Bluespec synthesis to automatically handle the control logic for the scheduling, arbitration and management of shared resources

• Algorithms
• Complex control and system interconnect
• Transactors
• Architectural Models
• Synthesizable verification

The advanced types, extreme parametrization and atomic transactions of BSV, unavailable in other design languages, enable it to create a high-level, yet transparent and precise, specification of the desired architecture quickly and predictably resulting in high quality implementations. Moreover, parametrization permits writing a single source code to encompass a wide variety of architectural choices, each of which may be more appropriate for different targets (e.g., mobile device vs. server). And with Bluespec’s PACLib (Pipelined Architecture Composers Library), one can build complex pipeline architectures in an easy “plug-and-play” manner by systematically composing powerful constructor building blocks.

With BSV’s extreme parametrization, a wide range of architectures can be rapidly explored from a single source code. And, since in BSV everything is synthesizable, all variants of design can be synthesized easily to run on FPGA/emulation platforms. This opens up new opportunities not only for implementation of FPGA designs, but also for realistic and fast modeling, exploration, validation and software development for ASIC designs well before silicon is available, often 3 to 4 orders of magnitude faster than simulation with SystemC models or prototype RTL.

Complex control and system interconnect

The only high-level abstraction for hardware concurrency, BSV’s atomic transactions are by far the single most powerful way to manage concurrency – and make it the only high-level synthesis solution suited to handling the toughest control and interconnect designs such as cache coherent memory systems, network-on-chip designs, processor architectures, DMA controllers and communication controllers.

With precise control over architecture, designers can explore and optimize for power, latency, or any other architecturally determined dimension of quality. As BSV can be used at any abstraction, you can start with a functional, even cycle-accurate model, and quickly refine it into a high quality implementation. And, since BSV is 100% synthesizable, you can validate your designs at orders of magnitude faster than simulation with SystemC models or prototype RTL.

Transactors

Synthesizable transactors are challenging to develop, which diverts development focus from core project activities and puts schedule at risk. Bluespec has a library of common transactors that can be used right off-the-shelf – and, if you need something different, Bluespec has the industry’s best solution for developing your own.

While C-based transactors are not synthesizable, BSV’s unique features are making it a popular choice for many companies building synthesizable transactors, which are central to emulation/FPGA-based verification flows:

• Atomic transactional rules and interfaces are excellent for expressing complex, fine-grain, heterogeneous parallelism, which is typical in control-dominated components (transactors, protocol engines, processors, caches, interconnects, DMAs, …)
• Very powerful FSM sub-language
• Excellent support for Multiple Clock Domains
• No subsetting for synthesis—all high-level features available in synthesizable code, even high-level models

C/C++/SystemC have been the default modeling languages. But they are weak at modeling hardware concurrency and they are not generally synthesizable. Consequently, they take too much time to develop, fall short on accuracy, and cannot run in emulators to fix simulation bottlenecks.

Bluespec provides the only solution that closes the gap between models and RTL implementations. Bluespec synthesizable models interoperate with RTL, can be rapidly explored for the optimal architecture, can be incrementally and selectively refined to a full implementation, and allow high-speed emulation at all stages of complex IP development.

Synthesizable verification

High-level verification languages and environments such as e/Specman, Vera and now SystemVerilog, as used in VMM or OVM, may be the state-of-the-art for writing test bench IP, but they are useless for developing models, transactors and test benches to run in FPGAs for emulation and prototyping. None of these languages are synthesizable. So engineers wishing to move verification assets onto FPGAs have been designing with RTL, the same old slow, resource-intensive and error-prone way.

With the powerful, 100% synthesizable capabilities of BSV, designers can leverage a modern high-level language for synthesizable verification IP. Engineers can design test benches, models and transactors at a high level of abstraction and with extreme reuse, but they can also synthesize them onto FPGAs – and they can do this as easily as they do today in simulation-only verification environments. Imagine running your test benches, models and transactors at tens of MHz.