BLUESPEC ADDS COSIMULATION TO ITS CYCLE-ACCURATE MODELS

– Supports both SystemC and Verilog Environments, Providing Engineers with Flexibility while Retaining Source-Level Debug Capabilities –

Waltham, Mass. – April 18, 2005 – Bluespec Inc., www.bluespec.com, developer of the only behavioral synthesis solution for control logic and complex datapaths, announced today it has added cosimulation capabilities to its model simulation technology that will allow hardware chip designers to utilize Bluespec’s cycle-accurate models in SystemC or Verilog modeling environments. This provides design engineers with the flexibility to leverage accelerated models in the most appropriate and preferred environment for a given stage in design.

“From modeling to RTL, Bluespec is bridging specifications, modeling and implementations to deliver a comprehensive ESL capability,” said George Harper, VP Marketing. “Bluespec gives you fast, cycle-accurate models that can be co-simulated in your existing environment. These cycle-accurate models not only help debug, but can be delivered to the system-level customer to accelerate software development or design-in.”

Bluespec’s EDA toolset generates Verilog RTL and cycle-accurate executables from a high-level design. The cycle-accurate models can be integrated into a Verilog System-on-a-Chip (SOC) design, back-annotated into a SystemC model or testbench or become part of a mixed SystemC/Bluespec model.

The cosimulation capabilities enable a heterogeneous design component environment to be easily simulated. With growing use of IP, it is essential that designers mix high-level design with existing IP blocks, at any level of abstraction. Bluespec will automatically generate all of the shims required for these models to co-simulate.

Availability
Bluespec's cosimulation support is available now.

About Bluespec
Bluespec Inc. manufactures an industry standards-based Electronic Design Automation (EDA) toolset that significantly raises the level of abstraction for hardware design while retaining the ability to automatically synthesize high quality RTL, without compromising speed, power or area. The toolset, the only one focused on control and complex datapaths, allows ASIC and FPGA designers to significantly reduce design time, bugs and re-spins that contribute to product delays and escalating costs. More information can be found on www.bluespec.com or by calling 781-250-2200.

Copyright 2005 Bluespec, Inc. Bluespec is a trademark of Bluespec, Inc. All other brands, products, or service names may be trademarks or service marks of the companies with which they are associated.

###