| In
The News
February 5, 2007
EETimes - Reusable IP added to ESL synthesis
Online Article by Richard Goering
January 11, 2007
Yahoo News - IEC Announces 2007 DesignVision Finalists Recognizing Best Tools and Products in Semiconductor Industry
Online Press Release
December 18, 2006
Deepchip - Wiretap email
Online Email Response by
Duraid Madina
December 2006
Chip Design - Can ESL Synthesis Make High-Level Modeling Relevant?
Online Article by Shiv Tasker, Bluespec
November 29, 2006
Electronic News - Hauck Hops to Bluespec from Faraday
Online Article by Colleen Taylor
November 27, 2006
Electronic News - Bluespec Creates Automated Path to HW/SW Validation
Online Article by Ann Steffora Mutschler
November 27, 2006
EETimes -
Virtual prototype support rolls out
Online Article by Richard Goering
November 13, 2006
EDN - Waiting for the Squid to Cook
Online Article by Shiv Tasker
November 10, 2006
EETimes - Low Power Raises the Heat
Online Article by Ed Sperling
October 28, 2006
EETimes - Bluespec, Satyam Computer alliance to expand presence in India
Online Article
October 25, 2006
Deepchip - INDUSTRY GADFLY: "the untold Gary Smith backstory"
Online Article by John Cooley
October 5, 2006
Deepchip - ESNUG - George explains his claim that Bluespec is ESL while Forte is RTL
Online Email by George Harper, Bluespec
September 28, 2006
EETimes - OCP-IP adds six members
Online Article by Dylan McGrath
September 26, 2006
Deepchip - Wiretap email
Online Email Response by George Harper, Bluespec
August 22, 2006
Electronic Design - The Move to Higher Levels of Abstraction
Online Article by Shiv Tasker, Bluespec
August 15, 2006
EETimes - ESL startup joins Synopsys partner program
Online Article by Dylan McGrath
August 10, 2006
Deepchip - Best of DAC 2006
Online Article by John Cooley
July 24, 2006
EETimes - Imperas tops analyst watch list
Online Article by Richard Goering
July 23, 2006
Gartner/Dataquest - Gary Smith lists Bluespec as one of his "What to see at DAC" list for 2006.
July 18, 2006
EETimes - OSCI adds 11 associate members
Online Article by Dylan McGrath
July 11, 2006
FPGA and Structured ASIC Journal - System-Level Slideshow; ESL Eases FPGA Design
Online Article by Kevin Morris
July 6, 2006
EE Times - Startups integrate ESL synthesis, power estimation
Online Article by Dylan McGrath
June 23, 2006
DeepChip - Everything Else EDA Census
Online Article by John Cooley
June 19, 2006
EDACafe - Bluespec - ESL Synthesis
Online Article by Jack Horgan
June 15, 2006
Electronique International - La voie pour la synthese au niveau systeme en SystemC est grande ouverte
Online Article by Cedric Lardiere
June 8, 2006
Electronic Design - Extensions drop SystemC into the hardware domain
Online Article by David Maliniak
June 2006
EDA Tech Forum - Techniques for low power at the system level
Online Article by George Harper, Bluespec
Components in Electronics - SystemC viable for harware design
Online Article by Dulcie Elliot
May 30, 2006
EE Times - Bluespec CEO: time to design, verify IC halved
Online Article by Richard Goering
Electronics Weekly - Bluespec adds synthesis to SystemC
Online Article by Harry Yeates
May 29, 2006
EE Times - SYNTHESIS TOOLS: CEO: time to design, verify IC halved
Online Article by Richard Goering
EE Times - A bridging model for ESL synthesis
Online Article by Rishiyur S. Nikhil, Bluespec
May 15, 2006
EDACafe - Buzz@DAC.2006
Online Article by Peggy Aycinena
May 12, 2006
EE Times - Panel: EDA and IP vendors subservient to consumer
Online Article by Nicolas Mokhoff
May 11, 2006
EE Times - Startup Bluespec updates ESL synthesis tool
Online Article by Dylan McGrath
May 2006
Network Systems Design - Using electronic system level (ESL) synthesis to design network systems
Online Article by George Harper, Bluespec
System Design Frontier Journal - Is hardware innovation over?
Online Article by Professor Arvind, MIT
April 28, 2006
DeepChip - A boatload of users critique Bluespec design
Online Article by John Cooley
April 1, 2006
Electronic Business - Startups grow up
Online Article by Bill Roberts
March 31, 2006
EE Times - Startup switches to assembly language development environment
Online Article by Clive Maxfield
March 21, 2006
FPGA and Structured ASIC Journal - Are you designing with too many significant figures?
Online Article by George Harper, Bluespec
March 20, 2006
Mass High Tech - New VC funds add luster to Bluespec's prospects
Online Article by Efrain Viscarolasaga
March 13, 2006
EE Times - Xilinx launches ESL initiative
Online Article by Peter Clarke
March 9, 2006
EE Times - ESL startup raises $4.5 million
Online Article by Dylan McGrath
Boston Business Journal - Bluespec lands $4.5M in second-round funding
Online Article
March 6, 2006
EE Times - Vendors warm to SystemVerilog
Online Article by Richard Goering
March 3, 2006
Electronics Weekly - Hardware design needs a software shift
Online Article by Simon Calder, SpiraTech
February/March 2006
Chip Design - There's No Prize for Taking the Long Road
Online Article by George Harper, Bluespec
February 22, 2006
EDACafe - Technical Paper on ESL Synthesis to be Presented at DVCon 2006; Case Study Showcases Bluespec Methodology for Processors
Online Article
February 1, 2006
EE Times - Startups say ESL adoption accelerating
Online Article by Dylan McGrath
Electronic Business - Nanotech "chips" mean explosive EDA growth
Online Article by Geoffrey James
January 20, 2006
EE Times India - Bluespec, Indian institutes partner on design methodology course
Online Article
January 17, 2006
EE Times - ESL provider joins consortium promoting IP interoperability
Online Article
January 10, 2006
Electronic Design - A Modest Proposal (featured in David Maliniak's January 10, 2006 EDA Alert)
Online Article by George Harper, Bluespec
January 5, 2006
EE Times -
MIT OpenCourseWare adds course on Bluespec methodology
Online Article
January 4, 2006
TechOnLine - 2006: The Year of Electronic System Level Synthesis
Online Article by Shiv Tasker, Bluespec
December, 2005
iDesign on Chip Design - There's No Prize for Taking the Long Road
Online Article by George Harper, Bluespec
November 28, 2005
EE Times - Verilog simulator becomes open-source item
Online Article by Richard Goering
November 16 , 2005
Programmable Logic DesignLine (PLDesignLine) - ESL even I can understand!
Online Blog by Clive Maxfield, author of How Computers Do Math
Programmable Logic DesignLine (PLDesignLine) - Performing rapid and safe evaluations at the architectural level
Online Article by George Harper, Bluespec
September 28, 2005
EDA Confidential - People: Bluespec announces that Bob Iannucci, Senior Vice President and Head of Nokia Research Center, has joined Bluespec's Board of Directors
Online Article by Peggy Aycinena
September, 2005
iDesign on Chip Design - You can't get there from here: a Yankee's lessons about EDA
Online Article by George Harper, Bluespec
August 18, 2005
Electronic Design - Synthesis attacks the abstract
Online Article by David Maliniak
June/July, 2005
Chip Design - When you have a hammer, everything's a nail!
Online Article by Bluespec
Chip Design - Product news: Multiple clock domains
Online Article by John Blyler
Chip Design - In search of an ESL design methodology
Online Article by Gary Smith
June 30, 2005
Deepchip - Industry Gadfly: My post-DAC debriefing with Pallab and Cliff (#23)
Online Article by John Cooley
June 13, 2005
EE Times - Bluespec targets low-power ESL synthesis
Online Article
June 6, 2005
EE Times - DAC drills down to the system level
Online Article by Richard Goering & Dylan McGrath
SOC Central - Don't forget the little guys!
Online Article by Max Maxfield
May 26, 2005
Electronic Design - DAC unleashes a torrent of tools and methodologies
Online Article by David Maliniak
May
23, 2005
EE
Times - EDA startup appoints Analog
Devices executive to board
Online
Article by Peter Clarke
April
18, 2005
EE
Times - Cutting a fast path to
semiconductors
Online
Article by Richard Goering
April 15, 2005
EE Times - Bluespec adds cosimulation to C models
Online Article by Dylan McGrath
April 4, 2005
EE Times - Semi startups continue to shake funding tree
Online Article by Nicolas Mokhoff
March 31, 2005
EDA Nation - An ESL State of Mind
Online Article by Peggy Aycinena
Electronic Design - Getting to a Higher Level
Online Article by David Maliniak
February 1, 2005
SOC Central - Are you building your ESL design flow on sand?
Online Article by George Harper, Bluespec
December
20, 2004
EE
Times - Bluespec synthesizes SystemVerilog verification assertions
Online
Article by Richard Goering
November
19, 2004
EE
Times - Bluespec gets $4.5 million
more in VC funding
Online
Article by Mike Santarini
November
15, 2004
EE
Times - Behavioral synthesis tied
to verification
Online
Article by Richard Goering
September
16, 2004
EDN
-
EDA tools for FPGAs break down the complexity
gridlock
Online
Article by Gabe Moretti
June
15, 2004
FPGA
Journal -
Cool and Groovy at DAC
Online
Article by Kevin Morris
June
8, 2004
EE
Times -
EDA vendors reveal plans for SystemVerilog
Online
Article by Richard Goering
June
1, 2004
EE
Times
-
EDA trends suggest turning point for chip design
Online
Article by Richard Goering
May
31, 2004
EE
Times -
High-level synthesis rollouts enable ESL
Online
Article by Richard Goering
May
10, 2004
Electronic
Design
-
Startup elevates SoC synthesis
Online
Article 
PDF(18K) by
David Maliniak
April
26, 2004
EDA
Cafe - Behavioral
synthesis
Online
Article
PDF(90K) by
Dr. Jack Horgan
April
5, 2004
EE
Times - Behavioral
synthesis crossroad
Online Commentary
PDF(834K) by
Richard Goering
March
31, 2004
EE
Times - Synopsys
forum updates SystemVerilog support
Online Article by Richard Goering
March
28, 2004
In
Play in EDA - Celebrities
for a new age
PDF(73K)
by Peggy Aycinena
March
24, 2004
In-Stat
MDR - Groundbreaking
Technology From MIT Fundamentally Alters Approach
To ASIC/FPGA Creation By Attacking Root Of Design
Issues
Information
Alert by Jerry Worchel
March
22, 2004
EE
Times - Breakthrough
nets startup high-level synthesis
Top Story by Richard Goering
Mass
High Tech - Bluespec
takes aim at next-generation chip design
Online Article by Jim Malone
February
5, 2004
EDN
- The
search for the perfect language
Online Article by Gabe Moretti
January
1 , 2004
India
New England - Bluespec
has designs on saving billions for semiconductor
industry
Online Article
PDF(149K)
by Mark Pickering
December
18, 2003
EE
Times -
Accellera accepts Bluespec SystemVerilog donation
Online Article by Richard Goering
December
15, 2003
EE
Times - Synopsys,
Cadence give nod to SystemVerilog changes
Online Article by Richard Goering and
David Roman
December
8, 2003
EE
Times - EDA
startup pioneers assertion-based synthesis
Top Story by Richard Goering
Mass
High Tech - Bluespec
banks $4 million in VC cash
PDF(2K)
by Matt Kelly
December
5, 2003
Boston
Business Journal - Software
maker Bluespec raises $4M in venture cash
PDF(11K)
by Tom Witkowski
EE
Times - Accellera
outlines major SystemVerilog enhancements
Online Article by Richard Goering
November
12 , 2003
EE
Times - Unannounced
EDA startups surface at ICCAD
The Buzz
by Richard Goering
|
