BLUESPEC TO SHOWCASE PRODUCTS, HD H.264 DESIGN DURING VLSI CONFERENCE 2007

– Demonstrations Planned of Video Decoder Designed With Bluespec by Indian Institute of Science Incubation Morphing Machines –

Waltham, Mass. – January 3, 2007– Bluespec Inc., developer of the only electronic system level (ESL) synthesis for control logic and complex datapaths in chip design, will demonstrate its product lines during the VLSI Conference 2007 (Booth #20) January 8-10, in Bangalore, India. A highlight of the Bluespec booth’s offerings will be a demonstration by Morphing Machines, an Indian Institute of Science incubation, of its high-performance multimedia, video decoder intellectual property (IP).

Used for virtual platforms, architectural exploration and ESL implementation, Bluespec comprises two product lines for the transaction-level modeling (TLM) and transaction-level design of application specific integrated circuits (ASICs) and field programmable gate arrays (FPGAs). The first is the recently announced and shipping ESE for SystemC. The other is the production-proven and popular BSV for SystemVerilog.

Morphing Machines will showcase an H.264/AVC/MPEG-4 part 10 baseline profile decoder completed in 11 man-months from product specification to prototyping in Altera Corporation’s DE2 Development and Education board, including reference code to FPGA partitioning and prototyping. The IP can be implemented in a system on chip (SoC) or FPGA to decode H.264 compliant video streams for applications ranging from consumer video, including Blu-ray and HD-DVD technologies, HDTV, digital multimedia broadcasting, medical imaging, and satellite imaging. Key features include:

• Highly scalable, for power and speed flexibility –– the high-performance, multi-level pipeline architecture supports HD at low clock rates for low-power applications or FPGA implementations but scales to support high-density video applications like medical imaging. The core supports 70 MPixels/sec at 50 MHz, meeting Level 4, and is capable of 4Kx2K frame sizes at 200 MHz.

• Extensible –– a transaction-level design based on Bluespec. The implementation is less than 20,000 lines of maintainable, and easily extensible, code

• Low gate count –– efficient implementation delivers competitive area results

• No CPU required –– the core is a complete hardware solution eliminating the need for external processors, accelerators or DSPs.

This FPGA-based design, completed with Bluespec ESL, placed third out of 140 teams from India, Australia and New Zealand in the Altera Nios II Embedded Processor Design Contest 2006. “Our designers are thrilled with their award in such a prestigious contest, and we credit Bluespec with helping us achieve this success,” notes Professor S. K. Nandy, Chairman and Director of the Morphing Machines Pvt Ltd. “Bluespec enabled the rapid high-level design of this high-performance, high-throughput decoder – in much less than half the time it would have taken with RTL. The Bluespec software helped the team make rapid design changes and enhancements, and enabled them to do true architecture space exploration.”

About Bluespec
Bluespec Inc. manufactures industry standards-based Electronic Design Automation (EDA) toolsets that significantly raise the level of abstraction for hardware design while retaining the ability to automatically synthesize high-quality RTL, without compromising speed, power or area. The toolsets, including the only ESL synthesis tools focused on control and complex datapaths, allow ASIC and FPGA designers to reduce design time, bugs and re-spins that contribute to product delays and escalating costs. More information can be found on www.bluespec.com or by calling (781) 250-2200.

Copyright 2006 Bluespec, Inc. Bluespec is a trademark of Bluespec, Inc. All other brands, products, or service names may be trademarks or service marks of the companies with which they are associated.

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