BLUESPEC'S SYSTEMVERILOG PROPOSAL APPROVED BY ACCELLERA TECHNICAL COMMITTEE

-- Bluespec's Tagged Unions and Pattern Matching Submission for SystemVerilog 3.1a Raises Level of Abstraction and Code Quality --

Waltham , Mass. , December 17, 2003 – Bluespec Inc., an Electronic Design Automation (EDA) tool company, today announced that its submission for enhancing SystemVerilog design was formally accepted last week by the Technical Committee of the Accellera standards organization . The submission addresses Tagged Unions and Pattern Matching for SystemVerilog 3.1a, the latest version of the design language being readied for release in June 2004. The new elements raise the level of abstraction for design and improve the expressiveness and readability of the SystemVerilog language. The result will be more concise, higher quality code, fewer errors and better formal verification, all while maintaining full capability to synthesize no compromise hardware.
 
"Bluespec's Tagged Unions and Pattern Matching enhances SystemVerilog for the hardware designer by making code more expressive and less prone to errors early in the design cycle, " said Vassilios Gerousis, Chair of Accellera's Technical Committee. "Accellera's SystemVerilog efforts have benefited from broad industry participation, and it is these types of submissions that continue to extend Verilog for high-level SoC design and verification."
 
A driver of worldwide standards for language-based design automation processes utilized by systems, semiconductor and design tools companies, Accellera was formed in 2000 to improve designers' productivity through a methodology based on both worldwide standards and open interfaces. Bluespec fully supports this notion, and has been involved since its inception with the effort to improve design standards in conjunction with Accellera. With their clean formal semantics, significantly elevated level of design with structures and unions, and reduced likelihood of errors, the underlying concepts of Tagged Unions and Pattern Matching have had strong support in many high-level languages for years. Since the language additions are fully synthesizable, both designers and verification engineers should benefit with accelerated design and reduced verification effort.
 
“We are very encouraged by the Accellera Technical Committee's recent acceptance of our proposed changes for the SystemVerilog language, as it validates that Bluespec's vision of hardware synthesis is in line with the market demands that motivated these improvements,” said Shiv Tasker, Bluespec CEO. “The emerging SystemVerilog language is a key component to Bluespec's technology, and we anticipate continued involvement with Accellera to create an industry standards-based design environment that significantly raises the level of abstraction while retaining the ability to generate hardware.”
 
"By bringing high-level programming concepts into the synthesizable language core, Bluespec's submission addressed Accellera SV-BC Committee's charter, enhancing the SystemVerilog language for hardware designers," said Johny Srouji, Chairman of the SystemVerilog Design Technical Committee.
 
About Bluespec
Bluespec Inc. manufactures an industry standards-based Electronic Design Automation (EDA) toolset that significantly raises the level of abstraction for hardware design while retaining the ability to automatically synthesize high quality RTL, without compromising speed, power or area. The toolset allows ASIC and FPGA designers to significantly reduce design time, bugs and re-spins that contribute to product delays and escalating costs. More information can be found on www.bluespec.com or by calling 781-250-2200.
 
About Accellera
Accellera is an electronics industry organization driving the worldwide development and use of standards required by systems, semiconductor, and design tools companies that enhance a language-based design automation process (www.accellera.org).
 
Copyright 2003 Bluespec, Inc. Bluespec is a trademark of Bluespec, Inc. All other brands, products, or service names may be trademarks or service marks of the companies with which they are associated.
 
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