GROUNDBREAKING TECHNOLOGY FROM MIT
FUNDAMENTALLY ALTERS APPROACH TO ASIC/FPGA CREATION BY ATTACKING ROOT OF DESIGN ISSUES

-- Term Rewriting Systems Technology Licensed to EDA Tools Developer Bluespec as Core of Flagship Product --

Waltham, Mass. – March 22, 2004 – Bluespec Inc., developer of the industry’s first high-level SystemVerilog-based Electronic Design Automation (EDA) toolset, announced today that the Massachusetts Institute of Technology (MIT) has granted an exclusive license of its groundbreaking Term Rewriting Systems (TRS) based synthesis technology for use as the foundation of the company’s EDA toolset. TRS is a computational model that enables high-level hardware synthesis with results, for the first time, that match hand-coded Register Transfer Level (RTL), fundamentally changing the way engineers can approach hardware generation.

Bluespec has wrapped the TRS model with SystemVerilog. This powerful combination provides an unmatched level of design simplicity, accelerating the time to a verified netlist by as much as 50 percent and dramatically reducing verification efforts.

“Before this technology, no one had succeeded in significantly elevating the level of design without compromising hardware implementation,” said Rishiyur S. Nikhil, CTO of Bluespec. “MIT’s TRS synthesis technology enables control logic generation on a correct-by-compiler construction basis – promising a fundamental change in ASIC and FPGA design. Now companies can eliminate the source of the most persistent design issues, expediting their time-to-market while limiting verification costs.”

TRS IS CORE OF CONTROL LOGIC GENERATION
With research foundations that trace back to the 1930s in mathematical logic theory, TRS represent the core of a new hardware generation approach developed in MIT labs by Professor Arvind, the Johnson Professor of Computer Science and Engineering, and his students. TRS consist of "terms" which describe hardware states, and "rules" which describe behavior. A "rule" captures both a state-change (an "action") and the conditions under which it can occur. The atomic semantics of TRS rules make it easy to debug highly concurrent and complex designs, making it ideal for composing large designs and for sub-dividing designs across teams. The MIT technology makes it possible to generate efficient hardware from a TRS-based design; it generates optimized circuitry for scheduling the rules, allowing many to “fire” simultaneously, while remaining faithful to the one-at-a-time semantics of TRS. MIT was granted a patent in July 2003 for this technology after demonstrating that TRS-based synthesis can significantly raise the level of abstraction for design engineers, providing a clear, unambiguous semantic model with well-understood transformations for delivery of higher-quality hardware.

Prior high-level Hardware Description Language (HDL) attempts specify a digital circuit in "behavioral" terms, without necessarily identifying the structure of the underlying circuit. For instance, SystemC supports such a behavioral specification approach; however, it has not been possible or feasible to synthesize effective digital circuits from such behavioral specifications.

Whereas other high-level synthesis approaches use software expressivity to describe circuit behavior, Bluespec uses software expressivity only to describe circuit structure; behavior is specified entirely by rules. By using full software expressivity in the static elaboration of structure, not in expressing behavior, Bluespec eliminates ad hoc limits such as “synthesizable subsets” in behavioral descriptions.

For the first time TRS elevate the design abstraction level while still implementing high-quality RTL. The patent represents a method of synthesizing a synchronous digital circuit by first accepting a specification of a system in which stored values are updated according to a set of atomic state-transition rules. This specification is internally and systematically represented with a TRS system. TRS semantics and transformations enable the efficient mapping of the input into scheduled, optimized RTL, where control logic is synthesized for correct-by-compiler construction.

“As hardware implementations become larger and more complex, the design process is becoming increasingly more time consuming and more exposed to human error – exacerbating design delays and driving exponential cost increases,” said Professor Arvind. “TRS-based synthesis was developed to attack the root of these design issues and has proven to shift the focus to where it needs to be – early in the design phase rather than in verification.”

About Bluespec
Bluespec Inc. manufactures an industry standards-based Electronic Design Automation (EDA) toolset that significantly raises the level of abstraction for hardware design while retaining the ability to automatically synthesize high quality RTL, without compromising speed, power or area. The toolset allows ASIC and FPGA designers to significantly reduce design time, bugs and re-spins that contribute to product delays and escalating costs. More information can be found on www.bluespec.com or by calling 781-250-2200. Copyright 2004 Bluespec, Inc. Bluespec is a trademark of Bluespec, Inc. All other brands, products, or service names may be trademarks or service marks of the companies with which they are associated.

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