| Title |
Summary |
Link |
| Bluespec
SystemVerilog Product Overview |
This
two pager provides an overview of Bluespec SystemVerilog,
including benefits, features, target applications
and technology. |
|
Automatic
Generation of Control Logic with Bluespec
SystemVerilog
(Small switch example)
|
This
technical white paper provides a basic introduction
to Bluespec through a sample design. It takes
a small switch and explains the Bluespec SystemVerilog
design, the generated Verilog, and scalability
considerations. |
|
| Are
You Building your ESL Foundation on Sand? |
This
is the complete version of a Bluespec article
that was featured as part of SOC Central's
February 2005 special topics focus on ESL
Design . The article contrasts how SystemC
and Bluespec raise design abstraction across
the following dimensions: structure, resources,
concurrency/coordination, and communication. |
|
| BSV
101: Designing a Counter |
This
is Bluespec's hardware equivalent of a "Hello
World!". If you want to get a
feel for building a simple design and testbench
using Bluespec's toolset and methodology,
this is a great tutorial. As it is
a hands-on, progressive walk-through of
a relatively small design, this document
is only intended as a tutorial and is not
directly intended to highlight Bluespec's
benefits. As summarized in the introduction:
This
tutorial aims to explore the basics of design
in Bluespec SystemVerilogTM (BSV). We assume
previous hardware design experince in Verilog
or VHDL, and some familiarity with the Unix
command line, and hope that, after you’ve
completed this tutorial, you will be able
to design, synthesize, and debug simple
circuits and testbenches in BSV.
|
|
| Butterfly
Switch |
This
document outlines the design of a highly parameterized
butterfly switch design (crossbar switch).
You’ll find this design to be both succinctly
written and fully synthesizable into a high-performance
implementation. This white paper includes
a description of the design problem as well
as the solution, including source code for
the design and testbench. |
|
Interra Systems, Inc.
Bluespec Testing Results: Comparing RTL Tool Output to Hand-Designed RTL |
This document discusses Interra Systems experience with Bluespec tools and the results of its tests comparing the quality of Bluespec’s RTL results with those of hand-crafted RTL designs. It looks at area and timing results across 25 designs. |
|
| Bluespec SystemVerilog for IP Delivery and Effective RTL Debug |
This document includes a sample design and corresponding Verilog RTL and highlights:
1. Why Bluespec SystemVerilog and its generated Verilog RTL make a terrific solution for the delivery of IP;
2. Why Bluespec's generated Verilog RTL code is straightforward to understand, debug and work with.
|
|
|
To
access the following additional papers,
please
self-register with the Bluespec website. |
| Design
Assertions: Bluespec Rules |
This
short overview describes design assertions:
the concept, the notation for rules, their
semantics and why they facilitate correct-by-construction
design. It also discusses various topics in
rule synthesis such as mapping into clocked
synchronous hardware, modularity, automatic
generation of control circuitry, and resource
management. |
|
| Timing
Closure White Paper |
This
white paper, entitled "Achieving Timing
Closure with Bluespec SystemVerilog",
outlines the advantages in using Bluespec
to achieve timing closure over Verilog and
VHDL. |
|
| Pipelined,
Parameterized, Priority Queue (P3Q) |
The
P3Q design is an example of a highly-parameterized
synthesizable hardware component with complex
control. This example illustrates that Bluespec
offers a way to describe synthesizable hardware
at a very high level, with a degree of abstraction
and safety comparable to the most advanced
languages. |
|
| Pong
Tutorial |
The
Pong Tutorial describes the design of the
Pong code example and includes a full copy
of the Pong source code as an appendix. |
|
If
you are interested in research papers, both
commercial and academic, in Bluespec, please
go to the Technology/Research
page.
|
