|
Bluespec
SystemVerilog
Bluespec SystemVerilog products enable ASIC and FPGA designers to appreciably reduce design time, bugs, verification resources and re-spins that contribute to product delays and escalating costs. Bluespec’s toolset delivers ESL synthesis without the compromises inherent in previous solutions. In contrast, it provides:
• Quality of results (QoR) comparable to hand-coded RTL
• Ease of verification debug by correlating simulation to source
While delivering an elevated level of design abstraction, Bluespec's ESL synthesis is much different from traditional behavioral synthesis:
• The goal is not to generate RTL from C – instead, the goal is to deliver design and verification productivity without the compromises of previous attempts
• Based on SystemVerilog, Bluespec leverages familiar hardware semantics to ease the learning curve for hardware engineers and ensure that hardware quality matches that of hand-coded
• Bluespec assumes the designer, not the tool, knows the best architecture and micro-architecture. Bluespec just provides a more productive environment for the designer to work
• With behavioral synthesis, RTL structure bore little resemblance to what the designer wrote. With Bluespec, the RTL structure directly correlates to the design. Module hierarchy and state elements are all specified by the designer and maintained – names correlate tightly between source and RTL. This ensures ease of debug
• Bluespec delivers a significantly raised level of abstraction without compromising area, power or timing
Benefits to the designer for using Bluespec:
• Accelerate design time to verified netlist by 50%
• Reduce both bugs and verification costs by 50%
• Retain flexibility to make architectural changes late in the design cycle
• Enable rapid timing closure
• Deliver a unified environment for modeling through to hardware generation
As the first effective ESL synthesis compiler and simulator, Bluespec’s toolset provides a unique mix of capabilities. The Bluespec toolset includes both the Compiler and Simulator:
Bluespec Compiler (BSC)
Key features:
• SystemVerilog with Bluespec atomic transactions
• Correct-by-compiler construction of control and datapath logic
• Generation of no compromise Verilog RTL
• Comprehensive static verification of designs to eliminate problems before simulation
• Code succinctness and static elaboration for high-level abstractness, 10:1 code compression, and code re-use
• Integrates into and with existing Verilog IP
• Rich library of design building blocks
• Integrated compiler algorithms and techniques:
o Modular compilation and design
o Automated and user-defined scheduling of hardware
o Scheduling visualization and feedback
o Resource assignment, optimizationfs
o Standard optimizations, including common sub-expression elimination and logic
Bluespec Simulator
Key features:
• Simulation of the high-level design
• 100% cycle accurate with Verilog RTL
• Visibility to Bluespec interfaces, state elements and design assertion rules
• Generates standard VCD files
Download a product overview.
Bluespec is committed to standardization and interoperability -- please refer to this page to learn more.
To find out more, please contact your sales person or fill out this form. | 
