Verification is taking more and more effort. Software development starts too late and typically gates when products can be shipped. Reuse has been more initiative than reality. Architectural exploration is almost always a luxury. And, as if that was not enough, things are only getting harder as chips get more complex. Semiconductor companies can easily spend $40M-100M getting to revenue with a chip.

Today’s hardware design node, which is too detailed and error prone, exacerbates these issues. It is based on the same core technology introduced 25 years ago: state-centric, synthesizable RTL with low-level, explicitly described control logic and event driven simulation. Because RTL is too detailed and error prone, there are too many bugs, late integration with verification and software, minimal reuse and expensive development that takes too long.

Bluespec’s provides a unique, innovative solution for the development of system, algorithmic and control IP that:

• Delivers 2X-10X faster system composition and implementation
• Provides extreme reuse
• Requires significantly less verification
• Enables software to be integrated much earlier and to be run faster in simulation and, even, on FPGAs

Bluespec has the industry’s only general purpose, high-level synthesis solution for developing system interconnects, algorithmic and complex control IPs.

Unlike other ESL solutions, Bluespec lets the designer express the architecture directly – which gives the designer 100% control, eliminates surprises, and ensures the best quality, without any added weight of implementation.