Challenge
Keeping Pace with 10X

With silicon capacity outstripping the ability for current generation EDA tools to keep pace, chip design teams face increasing challenges as design complexity and verification efforts explode:

• Delivering high-quality as more complex solutions map to more errors, more verification resources and more verification time

• Accelerating software development which is increasingly the critical path to ramping revenue

• Maintaining architectural and design flexibility throughout the design cycle to accomodate the numerous, inevitable changes

This demands a powerful hardware system development environment where:

• Initial approximate executable models can be developed very quickly

• Model execution is very fast, enough to run realistic software (such as booting an OS and running an application)

• Models can seamlessly support a continuously varying mix of subsystems at different levels of abstraction, from direct application code to instruction set simulators to behavioral models to production-quality implementations

• Models provide early, accurate feedback on performance measures (latency, bandwidth, resource contention, silicon area, clock speed, and power)

• Models can be quickly refined into production-quality implementations, easily exploring architectural alternatives along the way.  And, where this capability applies equally to complex control logic as with datapath designs

Is such an development environment possible?  Absolutely!  Bluespec is delivering it today. Designed for ASIC and FPGA designers, architects, modelers and verification engineers, the Bluespec toolsets synthesize high-level system descriptions into no compromise RTL. Based on SystemVerilog, Bluespec can be used to design production solutions beginning with specification and modeling of the hardware, with the ability to transform these specifications and models automatically to RTL for rapid evaluation or final designs.

Bluespec’s ESL hardware synthesis enables:

• Early, synthesizable models and testbenches for software teams, architectural analysis, and verification.  Bluespec provides a single environment for both models and implementations.

• More concise, efficient designs backed by comprehensive static verification for significantly reduced verification efforts

• Better designs, with architectural changes possible throughout the design cycle

• Extreme IP reuse

• High-quality RTL generation, without compromise

This is a tremendous challenge -- though one that Bluespec has proven to address.  Read user feedback and perspectives on their experiences and ways they have benefited at DeepChip:

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