As chip verification and software development monopolize more of the development cycle, simulation has become a fundamental bottleneck. Emulation and FPGA prototyping promise relief, but they have a reputation for being expensive, hard to setup and manage, and prone to significant testbench performance bottlenecks. SCE-MI (Standard Co-Emulation Modeling Interface) will help change this. SCE-MI is a standardized interface for co-emulation of a software testbench with a hardware model running in an emulation system or on an FPGA prototype. The SCE-MI 1.0 standard handles the data exchange between software and hardware as well as clock control of the design in emulation. Supported by most emulation providers, SCE-MI should greatly simplify emulation and FPGA prototyping – and make them significantly more accessible.

You should attend this webinar to learn about SCE-MI and how it:

• Eliminates the complexity of connecting software and testbenches with emulation platforms and FPGA-based boards
• Accelerates verification and software debug
• Promotes infrastructure portability and re-use

This is a one-hour, focused session introducing how SCE-MI, the industry standard for co-emulation, is most commonly used, covering:

• SCE-MI’s architecture, capabilities and typical use models
• Performance considerations for co-emulation
• How SCE-MI will be used in the future and what automation will be required beyond SCE-MI

The two biggest obstacles to emulation adoption are system complexity and cost, both of which SCE-MI addresses. The SCE-MI abstractions and automation mitigate some of the most vexing complexity challenges, and expansion of SCE-MI support into the commodity FPGA space makes their use in low-cost emulation solutions more practical. Attend to learn more! Please register via this web page!

Led by former MIT professor Rishiyur S. Nikhil, PhD, CTO of Bluespec

Rishiyur S. Nikhil is co-founder and CTO of Bluespec, Inc., which develops tools that dramatically improve correctness, productivity, reuse and maintainability in the design, modeling and verification of digital designs (ASICs and FPGAs). The core technologies consist of a language, BSV (Bluespec SystemVerilog), which enables very abstract source descriptions based on scalable atomic transactions and extreme parameterization, and tools for high-quality synthesis of BSV into RTL. Earlier, from 2000 to 2003, he led a team inside Sandburst Corp. (later acquired by Broadcom) developing Bluespec technology and contributing to 10Gb/s enterprise network chip models, designs and design tools. From 1991 to 2000 he was at Cambridge Research Laboratory (DEC/Compaq), including one and a half years as Acting Director. From 1984 to 1991 he was a professor of Computer Science and Engineering at MIT. He has led research teams, published widely, and holds several patents in functional programming, dataflow and multithreaded architectures, parallel processing, compiling, and EDA. He is a member of ACM and IFIP WG 2.8 on Functional Programming, and a Senior Member of IEEE. He received his Ph.D. and M.S.E.E. in Computer and Information Sciences from the Univ. of Pennsylvania, and his B.Tech in EE from IIT Kanpur.

To view the Webinar, please register here.