Synthesizable Models Enable Early Emulation for Complex IP
Emulate with hardware-accurate models well before RTL is available
Overview:
High-level modeling is essential for success during the hardware development of complex IP blocks. Specifications should be accurately modeled and thoroughly evaluated before implementation, and test benches must be capable of applying and evaluating realistic application stimuli.
C/C++/SystemC have been the default modeling languages. But they are weak at modeling hardware concurrency and they are not generally synthesizable. Consequently, they take too much time to develop, fall short on accuracy, and cannot run in emulators to fix simulation bottlenecks.
Bluespec provides the only solution that closes the gap between models and RTL implementations. Bluespec synthesizable models interoperate with RTL, can be incrementally and selectively refined to a full implementation, and allow high-speed emulation at all stages of complex IP development.
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