Benefits

Q&A

Will the quality of my results suffer?

Is it harder to debug with Bluespec?

How steep is the learning curve?

Will I be able to integrate Bluespec with my existing design flow?

Can I use my existing IP?

Are algorithms better implemented in C/C++?

How about tapeouts?

Bluespec provides the following key benefits:

• Much faster design and composition (and significantly lower development costs) – increase output by 2X-10X across the entire development cycle for: faster time-to-market, fewer resources, more iterations/features and/or better quality. Develop extremely reusable libraries.
  
  
• Rapid architectural exploration – evaluate a broad solution space; achieve optimal area, power, performance and/or timing.
  
  
• FPGA prototyping and emulation – reduces the complexities and cost of working with FPGA prototypes and emulation platforms. Provides better portability of infrastructure across platforms.
  
  
• Extreme IP reuse – easily develop designs that are parameterized on almost any feature or micro-architecture dimension. Verify proper IP functionality once, not at every instantiation. Simplifies interfacing to IPs.
  
  
• Significantly higher quality design – experience an order-of-magnitude fewer bugs: for less verification, higher quality, and earlier integration with verification, software or FPGAs.
  
  
• High speed simulation – provides a more scalable, higher simulation speed, whether using Bluesim, Bluespec’s native simulator of BSV, or FPGAs, which Bluespec makes much simpler and lower cost to use.

Q&A

Will the quality of my results suffer?

• Just the opposite - the quality of your results often improve with Bluespec.   RTL designers are experiencing 2X to 10X productivity gains with absolutely no compromise in quality of results.  Bluespec enables more effective and rapid architectural exploration. Often, Bluespec designers can explore the architecture space faster – or, can focus on architecture rather than implementation – with improved area, power, performance and/or timing.
  
  
• With Bluespec, designers own and 100% control the architecture and micro-architecture. A given micro-architecture will be comparable whether designed at a high level in Bluespec or at a detailed, low-level in RTL. So, Bluespec designers can match the quality of any RTL implementation – but much faster and with dramatically fewer bugs. Often, designers are able to come up with better architectures with Bluespec, because it promotes rapid exploration and enables designers to focus on architecture rather than low-level details.

Is it harder to debug with Bluespec?

• A huge advantage over alternative high-level approaches, Bluespec makes it efficient to debug, typically much faster than with RTL. Two key aspects enable this: 1.  Bluespec designers are 100% in control of the architecture and micro-architecture, and; 2. Bluespec focuses debug on atomic transactions whether it is performed at the source or RTL level.

Unlike any other approach, Bluespec generates well-structured, readable, interoperable and predictable Verilog RTL:

• Bluespec RTL directly correlates to Bluespec source, following the identical architecture and microarchitecture, and neither adding nor deleting state elements.
  
  
• Bluespec’s generated RTL code is organized with a consistent and clear structure. Design elements and comments are organized into clear groupings such as modules, interfaces, state elements, scheduling logic and combinational logic – this simplifies both the understanding of the generated code as well as the ease of making changes

• Naming can be controlled from the source and is passed through into the RTL.
  
  
• Comments, in addition to those automatically generated by the compiler, can be entered into the source for inclusion in the RTL addressing module headers, state elements, and rules.
  
  
• Synthesis is highly consistent and predictable, even across changes.

• Particularly for those selling IP, an active focus is required to ensure that the Verilog constructs and techniques will be accepted by the EDA tools with which it will be used. Bluespec automates the generation of Verilog RTL with proven, broad interoperability. Additionally, many Bluespec features, including automatic synthesis of control logic, reusable designs, and module composition, generate higher quality designs and make it easier to debug and fix designs.
  
  

Bluespec provides a complete design and debug environment, the Bluespec development workstation, which is an integrated graphical environment which includes advanced Bluespec analysis tools as well as third-party tools, including simulators, waveform viewers and editors.

How steep is the learning curve?

• Of course, adoption of any new technology involves learning new skills.  Bluespec provides tremendous resources to ease the transition, including a large library of off-the-shelf packages, a graphical design environment (Bluespec's development workstation simplifies tool usage and lowers the learning curve), and easy incorporation of existing RTL and C code.
  

• Most importantly, because of the dramatic productivity benefits of Bluespec, there are no opportunity costs.   In fact, even on their first projects, design teams typically achieve at least a 2X productivity improvement over RTL.   And the productivity continues to improve as team members become more proficient.

Will I be able to integrate Bluespec with my existing design flow?

• Absolutely. Bluespec can be adopted non-disruptively with completely manageable risk.  From models, designs and implementations, BSV produces fully compatible Verilog 95 RTL and/or SystemC executable models that feed directly into the existing EDA ecosystem of commercial simulators and gate-level compilers.
  
  
• Bluespec customers often integrate existing Verilog or VHDL IP into Bluespec designs – and, integrate Bluespec designs into Verilog or VHDL-based designs.
  
  
• With its powerful parameterization and static elaboration capabilities, Bluespec allows companies to avoid the challenges and costs for in-house, proprietary platforms constructed from C, C++, Perl, or TCL/TK tools wrapped around Verilog.

Can I use my existing IP?

• Bluespec provides powerful mechanisms to package existing Verilog, VHDL, and C/C++ blocks into a BSV design.

Are algorithms better implemented in C/C++?

Here are some recent quotes on automatic parallelization, the term describing parallelization of sequential code:

“... after 25+ years of research, we are no closer to solving the parallel programming problem ...
... Hence, I do not believe Auto-par will solve our problems”
- Tim Mattson, Intel

“Automatic parallelization? Forget about it, at least for performance-critical applications”
- Akash Deshpande, CTO of system design at ARC

Most off-the-shelf C codes (including the reference codes for all standard codecs like OFDM, H.264, ...) need significant rewriting for C-based synthesis tools in order to get reasonable HW quality. It’s a myth to “just write C code, and the tool will produce (good) hardware”.

And these re-writes typically have to be targeted at the nuances and capabilities of a particular tool.

BSV is very high-level, powerful hardware system design language that competes and typically outperforms C synthesis tools for algorithmic designs – but, BSV is also excellent for system interconnects and control-based IPs as well. Compared to C-to-RTL synthesis, a BSV implementation:

• Is universal (no limitations of “synthesizable subset of C”)
  
  • Can deal with complex control and parallelism
    
• Can result in better quality (area, timing)
  
  • Match hand-coded RTL with more predictability & in less time
    
• Can have fewer lines of source code – an HD-quality H.264 decoder was written in fewer than 10K lines of BSV
  
• Can interface easily into SoC contexts
  
• Can deal easily with crucial systems issues such as:
  
  • Optimized memory architectures (caches, prefetching, sharing, configuration, ...)
    
  • Clock control (power control)
    
• Can result in more flexibility, maintainability and reuse
  
  • Because of more powerful parameterization
    
• Can represent a whole family of microarchitectures with different members suitable for different contexts (area, speed, latency, throughput), from a single source code
  
  • Because of more powerful parameterization

Bluespec has a rich library (written in, and demonstrating the power of, BSV – they are not built-in and thus can be easily extended) of parameterized microarchitecture combinators that can be used to:

• Enable high-level expression of a design representing a family of microarchitectures
  
• Generate, through parameter selection, a different degree of pipelining, parallelism, iteration, resource reuse, etc. And, unique to BSV, Bluespec automatically synthesizes (because of atomic transaction semantics) the control logic for each microarchitecture.

How about tapeouts?
BSV is silicon-proven with many tapeouts and FPGA-designs. Bluespec’s first commercial tapeout was in 2006.