RTL design is based on the same core technology introduced 25 years ago: state-centric, with low-level, explicitly described control logic, and event-driven simulation. It carries around too much detail to be effective at the system level while being cumbersome at the implementation level. Some of the frustrations of RTL-based design include:

• High-level models cannot be refined to RTL, creating a debilitating equivalence gap between modeling and implementation.
  
  
• Simulation time is prohibitive. RTL models are accurate but prohibitively slow and available too late in the development cycle.
  
  
• RTL designers are bogged down by manually implementing concurrency in control logic, and cannot react fast enough to changing requirements.
  
  
• Bluespec improves productivity and quality at every level, not just in design, but also architecture, specification, verification and layout.

Bluespec provides:

• Powerful abstraction mechanisms at every level, from modeling through implementation. When designing with Bluespec , one works not just with registers, but abstractions above registers such as FIFOs, register files, and memories with various interface properties, out-of-order buffers, interconnects, caches, FSMs, etc.
  
  
• Interface methods allowing modules to change state within other modules, without requiring manual coding, configuration, and connection of external ports.
  
  
• A single modeling environment that eliminates the interoperability gap between the high-level model domain of architects and verification engineers and the low-level implementation domain of design engineers.
  
  
• Guarded atomic transactions to help designers manage concurrent access to shared resources.
  

BSV allows the designer to express very abstract and complex hardware structures succinctly and robustly, while producing optimal, efficient RTL code. In conjunction with simple and clean semantics, the Bluespec tools can assess program correctness and transform programs systematically from specifications to RTL including:

• Automatically identifying and avoiding potential race conditions
  
  
• Automatically identifying resource contentions
  
  
• Managing multiplexing, connectivity, and, if desired, arbitration of common resources
  
  
• Ensuring that multiple actions which must happen together, stay together
  
  
• Automatic generation of control logic
  

RTL designers are using Bluespec to escape the language limitations of Verilog and C. They are experiencing 2X to 10X productivity gains with absolutely no compromise in quality or results and they are attacking problems previously too complex for hardware description languages. BSV produces fully compatible Verilog 95 RTL models that feed directly into the existing ecosystem of commercial simulators and gate-level compilers.