Do you wish you could rapidly explore architectures for optimal area, power, performance and timing?

Would you use FPGA prototyping or emulation if it were less costly and easier to use?

Are you looking for 2X-10X faster system and IP implementation?

Are your verification initiatives stemming the demand for more resources and time?

What if you could achieve extreme reuse?

Are you doing multi-core simulations in the quest to achieve the best performance?

Today’s hardware design node is too detailed and error prone to address these needs. It is based on the same core technology introduced 25 years ago: state-centric, synthesizable RTL with low-level, explicitly described control logic and event driven simulation.

Software-centric solutions such as C/C++/SystemC offer higher levels of abstraction, but only by restricting designer control and predictability over the architecture, the responsibility for which shifts heavily to the capabilities of a tool instead of an engineer. Unfortunately, synthesis tools for sequential designs cannot compete with designers, except with a fairly narrow class of datapath designs that are limited in scope.

Bluespec's customers are choosing BSV for hardware design because it provides C++/Java-like levels of abstraction and clean semantics without obscuring architecture. BSV designers retain predictability and controllability over architecture, which is, in the end, the most important driver of implementation quality. This makes Bluespec the industry’s only general-purpose, high-level synthesis solution that can handle any level of abstraction and any module type, including system interconnect, algorithmic and control.

Used by the world’s leading semiconductor and systems companies, Bluespec's silicon-proven high-level synthesis toolsets for ASICs and FPGAs address the needs outlined above by enabling:

• Fast modeling – design teams are using Bluespec to execute their software models orders-of-magnitude faster than possible in software on multi-core processors
  
  
• Architectural exploration and modeling – design teams are using Bluespec for early software models and rapid architectural refinement and exploration
  
  
• FPGA Prototyping and Emulation – design teams are using Bluespec to develop high-level testbenches, transactors and models that are automatically synthesized into FPGA prototypes or emulators for orders-of-magnitude faster verification and modeling on lower cost platforms
  
  
• System and IP design – design teams have consistently achieved at least a 2X productivity improvement over RTL on their first projects and are benefitting from extreme reuse.

Learn more about Why Bluespec:

Silicon-Proven Technology

Benefits and Q&A

vs. RTL

vs. C/C++/SystemC