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White Papers
Synthesizable Models Enable Early Emulation
 
Delivering Synthesizable Verification IP for Test Benches
 
Emulation: Enabling it on Every Desktop
 
High-Level “plug-and-play” specification, modeling, and synthesis of algorithms using Bluespec’s PAClib
 
Bluespec vs. C/C++/SystemC for Modeling, Model Refinement & Design Imlementation

 
White Papers
10-minute Technical Overview of Bluespec
 
On-Demand Detailed Technical Overview Presentation on Bluespec, its Solutions, and Core Technology
 
Designing Synthesizable Transactors and BFMs
 
SCE-MI: Enabling Faster IP Verification with Emulation & FPGA Prototyping

 


Products

Bluespec products are all about Building the Right Thing™. And today, that typically means building the right architecture – for power, performance, area, latency, or even time-to-market. Bluespec enables the fastest expression and exploration of architecture and microarchitecture. And, because Bluespec is 100% synthesizable, Bluespec enables the fastest evaluation of architecture. While you’ll find a detailed list of products below, Bluespec’s products are focused in two solution areas:
  • The industry’s first Synthesizable Virtual Platform and Models for SoC System & IP modeling, development and system integration
  • High-level synthesis with the industry’s only hardware concurrency abstraction above RTL, with 100% architectural transparency, for synthesizable:
    • Models, transactors, test benches & implementations
    • Complex control, system interconnect & algorithms
 

Core Technology

Bluespec Core Technology
Product Description
Bluespec Compiler (BSC) Compiles a high-level model, transactor, test bench or implementation into Verilog RTL or SystemC
Bluespec Simulator (Bluesim) Simulates Bluespec designs 5X-20X faster than RTL
Bluespec Development Workstation (BDW) Provides a high-level GUI-based development environment for the design, analysis and debug of Bluespec designs
emVM Provides debug, instrumentation & co-emulation for easy emulation of synthesizable models and legacy RTL with third-party FPGA boards/emulators
 

SVP

Synthesizable Virtual Platform (SVP)
Product Description
ARM9 SVP ARM9 ISS-based virtual platform that runs at high-speeds, integrating models & RTL in emulation
AHB Transactor Connects from TLM API on host to AHB bus in emulation (master or slave)
AXI Transactor Connects from TLM API on host to AXI switch in emulation (master or slave)
APB Transactor Connects from TLM API on host to APB bus in emulation (slave)
UART Transactor Connects console on host to UART in emulation
Memory Model Transactor Provides large, configurable memory model with storage in host or external memory. Model uses on-emulation cache for optimal performance.

10/100/1000 Ethernet Transactor

(in development)

Connects from TLM API on host to Ethernet interface in emulation (master or slave)
Custom Transactors BSV can be used to develop customized, highly complex transactors in a fraction of the time of hand-coded RTL

 
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